The authors introduce the multi-component seismic monitoring system AETA (acoustic & electromagnetic testing all in one system). The results of experiments in Yunnan, Sichuan, Tibet, Hebei, Beijing and Guangdong prove that the system AETA has the proper sensitivity with low cost and is easy to be installed. Meanwhile, the raw data and feature data refined from raw data have a good indication of earthquake. More subsequent experiments will be organized in west of China, capital circle of China and Taiwan Strait for deep research on effect of prediction.

Aiming at the requirements of modern high performance embedded system with high speed Serial RapidIO (SRIO) interconnect, a SRIO protocol controller IP with AXI interface is proposed. The hardware design of SRIO IP is implemented on the Xilinx XC5VLX220-FF1760 FPGA device. The proposed SRIO IP implemented with reasonable hardware architecture and some key design thoughts, can improve the speed of information collection and the real-time quality of data transmission. Meanwhile, the SRIO IP with resort to AXI bus can be more easily integrated into an SoC chip, which can also provide higher bandwidth for data transmission inside the chip. Consequently, the multi-DSP inside the FPGA device with the proposed SRIO IP can stably work at a very high reading/writing rate of 3.125 Gbps for each channel, which shows the performance of the proposed SRIO IP.

According to the hardware Trojans inserted during design and fabrication, the authors provide a new model of Trojan. New model is based on a finite state machine which is more difficult to trigger and detect than those based on combinational circuits. Also, the locations in target circuits to insert Trojans are considered to avoid being detected using path delay fingerprint method. S349 circuit from ISCAS’89 benchmark circuits is chosen as the target circuit. Functional simulations are performed and delay information is simulated. The results show that this type of hardware Trojan is difficult to activate and the insertion method is effective to hide delay information.

The authors establish an advanced macro-model that can be used to denote the device behaviors of ferroelectric field effect transistor (FEFET) including the dynamic overturn and the double threshold voltages transfer behaviors. The proposed advanced macro model with the simple and easily extracted model parameters can be performedin the HSPICEenvironment. The simulations show that the model can well fit the published experimental data. The proposed model can be used in the design and optimization of FEFET-based dynamic randomaccess memory circuits.